1. Technical Field
The present disclosure relates generally to hybrid sigma-delta converters and, more particularly, to efficient hybrid sigma-delta converters.
2. Related Art
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Applications involving signal processing such as modern communication systems require high accuracy (e.g. 12-14 bit) and high speed (e.g. tens of Megahertz) analog-to-digital converters (ADCs) and/or digital-to-analog converters (DACs). Sigma-delta modulation is a technique used in over-sampling converters in order to achieve high resolution and low distortion. Sigma-delta converters can be implemented using continuous-time circuitry and/or discrete-time circuitry. Sigma-delta converters utilizing a combination of continuous and discrete-time circuitry are known as hybrid sigma-delta converters.
Referring now to FIG. 1, an exemplary hybrid sigma-delta ADC 10 is shown to include a summer 12, a loop filter module 14, a quantization module 16, a first feedback DAC 18, and a second feedback DAC 19. The summer 12 receives and sums an analog input signal transmitted from an external device (not shown) with an output of the DAC 18. The loop filter module 14 receives an output signal (i.e., the summed input) of the summer 12.
The loop filter module 14 of the hybrid sigma-delta ADC 10 includes a continuous-time (CT) integration circuit 20, a discrete-time (DT) integration circuit 22, and a summer 23. The CT integration circuit 20 and the DT integration circuit 22 each typically comprise one or more continuous-time integrator circuits and one or more discrete-time integrator circuits. The CT integration circuit 20 processes the analog input signal. The summer 23 receives and sums the analog output signal of the CT integration circuit 20 with the output of the second feedback DAC 19. The output of the summer 23 is converted to a discrete-time signal and further processed by the DT integration circuit 22.
The output of the DT integration circuit 22 (i.e., the output of the loop filter module 14) is communicated to the quantization module 16. In various embodiments, the quantization module 16 may include a one bit ADC, though other types of quantization circuitry are contemplated. The output of the quantization module 16 forms the output data of the hybrid sigma-delta ADC 10. Additionally, the quantization module 16 communicates the output data to the first feedback DAC 18 which then converts the output data to an analog signal. The first feedback DAC 18 transmits the analog signal to the summer 12. The output of the quantization module 16 is also transmitted to the second feedback DAC 19.
Through the combination of CT input stages and DT filters, hybrid sigma-delta ADCs are able to precisely “shape” noise (e.g. quantization noise) generated during processing of the input signal. Additionally, hybrid sigma-delta ADCs feature superior anti-alias characteristics based in-part on the CT filter stages which often lessen the need of other anti-alias filters is specific applications. However, the DT filter incorporated within a hybrid sigma-delta ADC includes an intrinsic sample-and-hold (S/H) stage which can impose differential and common mode stress on the preceding CT stage within the hybrid sigma-delta ADC thereby causing a degradation of the overall Signal to Noise and Distortion Ratio (SNDR) performances of the hybrid sigma-delta ADC.